Non-volatile phase-change memories (PCMs) incorporate materials that have the ability to switch between phases having different electrical characteristics. For example, these materials can switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase, and the two phases are associated with resistivities of considerably different values, and consequently with a different value of a stored data. For example, the elements of Group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimonium (Sb), referred to as chalcogenides or chalcogenic materials, can be advantageously used for manufacturing phase-change memory cells. The phase changes are obtained by increasing locally the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as heaters) set in contact with respective regions of chalcogenic material. Selection devices (for example, MOSFETs), are connected to the heaters, and enable passage of a programming electrical current through a respective heater. The electrical current, by the Joule effect, generates the temperatures necessary for the phase change. During reading, the state of the chalcogenic material is detected by applying a voltage that is sufficiently low as not to cause a marked heating, and then by reading the value of the current that flows in the cell. Since the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and hence determine the data stored in the memory cells.
Non-volatile memories include an array of memory cells organized in rows (wordlines) and columns (bitlines). Each memory cell is formed, in the case of PCMs, by a phase-change memory element and by a selector transistor, connected in series. A column decoder and a row decoder, on the basis of logic address signals received at the input and more decoding schemes, enable selection of the memory cells, and in particular of the corresponding wordlines and bitlines.
The column decoder may include analog selection switches (comprised of transistors), which receive on their respective control terminals the address signals. The selection switches may be organized according to a tree structure in hierarchical levels, and their number in each hierarchical level is linked to the organization and to the size of the memory array. The selection switches, when enabled, allow the selected bitline to be brought to a definite value of voltage and/or current, according to the operations that it is desired to implement. In particular, a current path is created between a programming stage or a reading stage and the bitline selected. The current path is defined by the series of a certain number of selection switches, and is the same (within the memory array) both for the programming stage and for the reading stage. In particular, upstream of the current path, a selector is generally provided for associating the path alternatively with the programming stage or with the reading stage. Generally, the bitline-biasing voltages for reading operations are generated inside sense amplifiers used for reading the data in the reading stage, and the bitline-biasing voltages for writing operations are generated inside purposely provided programming drivers in the programming stage. The sense amplifiers carry out reading of the data stored in the memory cells by comparing the current that flows in the memory cell selected with a reference current that flows in a reference cell.
In the specific case of PCMs, in order to carry out a reading operation, voltages of a low value, for example between 300 mV and 600 mV, and currents of a standard value, for example in the region of 10-20 μA, are used. The voltages for carrying out writing are typically higher that the value for reading, for example, approximately 2 V higher than the voltage used for the reading operations. In addition, high currents, for example in the region of 600 μA, are used. In addition, a fast settling in the column coding is used during reading.
In PCM memories, sense amplifiers may include three stages. The first and second stages are typically differential stages, which serve as a current integrator and comparator, respectively. The third stage is a set-reset (SR) latch, which latches and converts a differential input into a single ended output. A shortcoming of this type of sense amplifier is that static current is always present in one of the arms of the comparator. In addition, relatively large precharge times are required, which leads to reduced throughput and longer access times.
Another example of an existing sense amplifier may include a differential I/V converter and a comparator, which is designed to bias the bit line directly from the supply voltage (VCC). The differential structure rejects read-while-write and supply noise occurring during the cell read operation. A bitline discharge-after-read feature may be implemented to reduce the error introduced by the wordline rise. For a multiple set cells pattern on the same wordline, the higher current injected in the selected wordline by the set cells increases the voltage, thereby affecting values of weak set cells and reset cells. Lowering the corresponding bitline after a set cell is detected may reduce this effect. However, a shortcoming of this type of sense amplifier is that the static current is cut only after the output is sampled by the flip-flop circuit at the end of the read cycle, thus, high current consumption is experienced until the output is sampled.
In addition, reliability is a prime concern for PCM cells for retention of correct data for a specified endurance cycle. The over voltages on the bitlines in existing sense amplifiers for long durations has a negative impact on endurance.